1. Technical Field
The present invention relates generally to communication link circuits, and more particularly, to digital signal transmitters having selectable drive capability and power consumption.
2. Description of the Related Art
Interfaces between present-day system devices and also between circuits have increased in operating frequency and complexity. In particular, high-speed serial interfaces include transmitters and receivers that typically consume relatively large amounts of the power budget of an integrated circuit. However, depending on channel conditions and parameters, the maximum output signal level of a transmission circuit may not be required for proper signal reception at the remote end of the interface. For example, the channel physical length may be shorter in some applications than in others, reducing signal degradation and thereby reducing transmit power requirements for the same receiver complexity.
Due to limited design resources and the need to satisfy the requirements of multiple interface applications, customers and channel conditions, transmitters and receivers within above-described interfaces are typically designed for the worst-case bit error rates and environmental conditions, leading to relatively complex receivers and high power transmitters. As a result, it is not always possible to provide a transmitter having lower power consumption when a high channel quality is available.
The above-incorporated Patent Application discloses an interface in which the transmitters and receivers have adjustable and/or adaptive parameters for finely tuning an interface to manage power consumption. One of the controllable parameters is the transmitter power level of the interface driver circuit(s). However, typical transmit power adjustment performed by changing the driver voltage and/or current levels is not always a preferable mechanism to adjust transmit power. Communications links within and between computer subsystems have reached bandwidths of between 5 gHz and 10 gHz and interface frequencies can be expected to increase in the future. Driver circuits operating at such high frequencies do not typically scale operation well over voltage or bias current adjustments, as internal impedances change with such adjustments causing mismatch and loss of power. Delay also typically increases with reduced transmitter power, compromising the integrity of the data window.
Transmitter drivers as described above are not generally simple digital buffers or inverters that switch power rail levels using an effectively near-zero impedance onto the interface line, but are typically linear driver circuits providing multiple stages of amplification or switches having progressively increasing and controlled signal current levels. The cascaded driver circuits progressively raise the power level of the signals internal to an integrated circuit or subsystem to the level required for transmission across the interface channel. Such complex circuits are susceptible to impedance changes due to power level adjustment and therefore such adjustment may not result in optimum performance for a given power consumption level. For example, if the mismatch between stages and at the input of the driver circuit increases when the transmit power level is dropped, the transmit power decrease will not be linear. Such non-linearity indicates an inefficiency of the driver at the lower power level. Similarly, if the transmitter is designed so that impedance matching is ideal at the lower power level, then at higher power consumption levels, the output power will not provide a linear increase with the consumption level. Delay necessarily increases with decreased signal levels through the stages due to device capacitance changes and charge effects relative to the reduced signal strength.
It is therefore desirable to provide an interface transmitter circuit having selectable power consumption that is efficient in both high and low power modes.